Semiconductor structure with coincident lattice interlayer

ABSTRACT

A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane surface. An atomically stable two dimensional crystalline film resides on the epitaxial insulating layer with a coincident lattice match to the insulating interlayer. Methods of fabrication are disclosed. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

CROSS REFERENCE TO RELATED DOCUMENTS

This application is related to and claims priority benefit of U.S.Provisional Patent Application No. 60/975,299 filed Sep. 26, 2007 whichis hereby incorporated herein by reference.

COPYRIGHT NOTICE

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BACKGROUND

Graphene is a two dimensional counterpart to graphite in that graphiteis composed of alternating stacking arrangements of graphene-likelayers. Graphene's carbon crystalline structure makes it an idealcandidate for use in fabrication of many electronic components. However,in order to realize the full potential of graphene and other atomiclayer structures in this application on a commercial scale, techniquesmust be developed which permit stabilization of single layers oncrystalline substrates.

BRIEF DESCRIPTION OF THE DRAWINGS

Certain illustrative embodiments showing organization and method ofoperation, together with objects and advantages may be best understoodby reference detailed description that follows taken in conjunction withthe accompanying drawings in which:

FIG. 1 shows a sketch of a method for growing one or more crystallinegraphene layers on a substrate such as silicon consistent with certainembodiments of the invention.

FIG. 2 is a cross-sectional sketch showing an embodiment consistent withcertain implementations of the invention using CaF₂.

FIG. 3, which is made up of FIGS. 3A, 3B, 3C and 3D shows fouradditional embodiments consistent with the invention involving theaddition of a conducting layer.

FIG. 4 depicts a process flow chart depicting the basic processes usedin fabricating structures as described herein consistent with certainembodiments.

DETAILED DESCRIPTION

While this invention is susceptible of embodiment in many differentforms, there is shown in the drawings and will herein be described indetail specific embodiments, with the understanding that the presentdisclosure of such embodiments is to be considered as an example of theprinciples and not intended to limit the invention to the specificembodiments shown and described. In the description below, likereference numerals are used to describe the same, similar orcorresponding parts in the several views of the drawings.

The terms “a” or “an”, as used herein, are defined as one or more thanone. The term “plurality”, as used herein, is defined as two or morethan two. The term “another”, as used herein, is defined as at least asecond or more. The terms “including” and/or “having”, as used herein,are defined as comprising (i.e., open language). The term “coupled”, asused herein, is defined as connected, although not necessarily directly,and not necessarily mechanically.

Reference throughout this document to “one embodiment”, “certainembodiments”, “an embodiment”, “an implementation”, or similar termsmeans that a particular feature, structure, or characteristic describedin connection with the embodiment or implementation is included in atleast one embodiment of the present invention. Thus, the appearances ofsuch phrases or in various places throughout this specification are notnecessarily all referring to the same embodiment. Furthermore, theparticular features, structures, or characteristics may be combined inany suitable manner in one or more embodiments without limitation.

The term “or” as used herein is to be interpreted as an inclusive ormeaning any one or any combination. Therefore, “A, B or C” means “any ofthe following: A; B; C; A and B; A and C; B and C; A, B and C”. Anexception to this definition will occur only when a combination ofelements, functions, steps or acts are in some way inherently mutuallyexclusive.

The term “coincident lattice” as used herein is defined as a structurewherein the lattice parameters of two crystalline materials are bothintegral factors of the lattice spacing for a coincident lattice betweento two materials. The coincident lattice structure results in a nearepitaxial match (generally within a few percent, and less than about 10percent) between the two materials at some distance greater than orequal to the larger lattice parameter of the two materials. Perfectcoincidence sites between an epitaxial layer with a lattice spacing ofa_(e) and a substrate with a lattice spacing of a_(s) would occur whena_(e)/a_(x)=m/n, where m and n are both positive integers. If m were toequal (n+1), there would be one extra lattice plane in each unit cell ofthe coincidence site lattice.

In the present discussion, {111} means the family of planes and includes(111), (−111), (−1−1−1) . . . , etc., and <110> means family ofdirections as is conventionally defined in materials science.

Carbon nanostructures in the form of fullerenes and nanotubes have beenwidely studied due to their impressive electrical properties andstability; however, the zero and one dimensional nature of the materialshas made incorporation of these materials into traditional electronicdevice architectures difficult or impractical in many applications. Twodimensional crystalline sheets made up predominantly of carbon andcommonly referred to as graphene, can be atomically bonded into a sheetlike structure as thin as one atomic layer in width. These materials areexpected to possess many of the desirable electrical properties as itslower dimensional counterparts and their two dimensional nature is moreapplicable to incorporation into electrical device structures than itslower dimensional counterparts. Graphene is also a two dimensionalcounterpart to graphite in that graphite is composed of alternatingstacking arrangements of graphene-like layers.

Unfortunately the methods currently being used to create two dimensionalcrystalline sheets of graphene are either not compatible withlarge-scale production technologies or produce rather mediocre qualitymaterial. For example, the first demonstrations of stable graphene filmswere created by mechanical exfoliation of highly oriented pyrolyticgraphite (HOPG) substrate. The crudest example of this method is tostick a piece of adhesive tape on the surface of an HOPG substrate whichadheres to surface layers on the HOPG and subsequently removes them fromthe substrate when the tape is peeled back. While this method enablesrelatively high quality graphene crystallites to be peeled off thesubstrate, unfortunately the size of the crystallites tends to be lessthan 100 μm on average. This technique clearly has very limitedlikelihood of being scalable to produce large scale wafer coverage(e.g., eight inches or larger).

Graphitization of silicon carbide (SiC) surfaces from thermaldecomposition reactions can also be achieved. The surface can bedecomposed through vacuum annealing to sublime silicon atoms from thesurface thereby leaving a carbon rich surface that reorders to formgraphene layers on the surface. However, the underlying interface tendsto be carbon rich, to contain portions of sp³ bonded carbon, and tocontain a number of silicon vacancies at the interface. SEM images ofthe graphene surfaces have also shown random defects and/or deposits,and unfortunately there is currently no clear understanding from wherethese undesirable features originate. Although a number of electricalmeasurements taken from surfaces prepared in this manner have beenpromising, it is unlikely that such a method can ever prepare anatomically abrupt interface with SiC due to the diffusion profile ofsilicon that result from the decomposition reactions. In addition, sincegraphene and graphene-based devices are expected to be extremelysensitive to small changes in thickness and bonding, it is doubtful thatuniform high quality device structures can be produced across a fullwafer using this method.

It has also been shown that the direct growth of carbon on crystallinesilicon {111} surfaces using acetylene (C₂H₂) as the carbon sourceresults in the formation of silicon carbide films for growthtemperatures between 600° C. to 700° C. and in the formation of a carbonrich silicon carbide (SiC_(x)) surface as the growth temperature isincreased from 700° C. to 900° C. The higher temperature growth isclosely related to the decomposition method previously described exceptin this method the interface is governed by the indiffusion of carbon.The result is that the same interfacial problems that arise in thesilicon carbide decomposition method also occur in the carbon depositionmethod.

Plasma enhanced chemical vapor deposition of carbon crystalline silicon{111} using methane (CH₄) as the carbon source can result in theformation of a reacted silicon carbide interface with an amorphous C—Hlayer on top. But, thus far there is no known report of either grapheneor graphite growth on silicon surfaces without the formation of somesilicon carbide and bonding at the interface. For use in electricaldevices, it is desirable to have a method where these reactions can beeliminated.

Hence, in order to realize the potential of stable two dimensionalcrystalline graphene in electronic applications, a reliable mechanismfor creating the films and minimizing substrate reactions is needed thatis compatible with large-scale production methods. So far no such methodis known to exist. Embodiments and implementations consistent with thisinvention relate to the fabrication of semiconductor basedheterostructures that include an electrically insulating crystallinelayer on a crystalline substrate such as a silicon substrate tofacilitate growth of a two dimensional crystalline film of one or moreatomic layers of graphene or other carbon based crystal.

In accord with certain example implementations, a method is provided forfabricating graphene films of one or more layers on crystalline siliconsubstrates where an electrically insulating crystalline interlayer isused to provide a stable template for nucleation and growth of a twodimensional crystalline graphene layer(s). The method makes it possibleto use the crystalline structure and symmetry of the {111} plane insilicon as a template to assist the nucleation and growth of twodimensional graphene films while eliminating undesirable interfacialreactions between silicon and graphene. An electrically insulatinginterlayer also provides for isolating the conduction channels of thetwo dimensional crystalline graphene layer(s) from the starting siliconmaterial where desired.

In accord with certain example implementations, crystalline graphenefilms can be grown on crystalline substrates such as crystalline siliconsubstrates by use of an insulating interlayer thereby combining theelectrical advantages of graphene with traditional silicon-based CMOS(or similar) technologies. The method can be scaled to allow depositionover any surface area of single crystalline wafer that can be produced.Many advantages of such a production method and the resultant structurewill be apparent to those skilled in the art upon consideration of thepresent teachings.

Example embodiments consistent with the present invention address theproblem of how to fabricate crystalline graphene layers on crystallinesubstrates such as crystalline silicon substrate. Silicon is the currentsubstrate of choice for device manufacturing due to the significantinfrastructure and technological knowledge base that has beenestablished over the years (but other crystalline substrates,interlayers and carbon based layers may also be suitable), and thereforesilicon will be used in the illustrative examples herein. In thiscontext, the term “insulating” refers to electrical insulation and meansthat no significant conduction occurs to the substrate, where suchsignificance may be application dependent. Generally, however, theelectrical conductivity of the insulating layer should be much less thanthe electrical conductivity of the carbon based layer.

The {111} surfaces of Si have a threefold crystalline symmetry that iscommensurate with the six-fold surface symmetry of graphene. Si {111}surfaces contain a Si—Si in-plane spacing of 3.84 Å, which is about 1.57times larger than the ring-to-ring spacing in graphene, and is normallytoo large for direct epitaxial growth. However, a 26.9 Å coincidentlattice between the Si {111} surface and graphene reduces the mismatchto less than 0.3% in the <110> directions. Graphene is capable offorming long range coincident lattice matches with the underlyingsubstrate, presumably due to the weaker van der Waals bonding across theinterface. The coincident lattice also provides graphene with amechanism to minimize direct atom to atom bonding to the material onwhich it is deposited and permits the formation of surface corrugationsthat help stabilize the film.

One substantial problem with graphene growth directly on silicon is thatsilicon is not thermodynamically stable during carbon deposition andreacts to form undesirable SiC_(x) species. The {111} surface of siliconalso has the problem that the surface silicon atoms have partiallyfilled electron orbitals that are not electrically stable and whichtherefore dimerize. This dimerization causes the surface structure toreconstruct into a charge neutral configuration. Additionally Si is notsufficiently insulating to form a base layer in all graphene devicestructures. Use of an intermediate layer in accord with implementationsconsistent with this invention ameliorates each of these problems whilestill utilizing the symmetry and lattice spacing in silicon for graphenegrowth.

FIG. 1 shows a simple schematic illustrating a macroscopic view of alayered construction of graphene on crystalline substrate 2 such as asilicon crystalline substrate with an intermediate layer 4. An epitaxialinsulating interlayer 4 is deposited on a crystalline silicon layer 2prior to the growth of a graphene layer 6 or layers. The growthorientation 8 is perpendicular to the surface of the crystalline siliconlayer and within 10 degrees (and preferably much less) of a <111>direction in the crystalline silicon layer. The epitaxial insulatinginterlayer should maintain an epitaxial alignment with the crystallinesilicon layer and have a 3n fold surface symmetry where n is an integer.The epitaxial alignment and symmetry constraints permit the epitaxialinsulating interlayer to maintain the favorable structural template inthe form of a coincident lattice established by the silicon layer fornucleation and growth of the graphene layer. Additionally the epitaxialinsulating interlayer forms a sufficient diffusion barrier to bothcarbon and silicon at temperatures up to 250° C. to keep silicon andcarbon separated and consequently prevented from reacting duringdeposition and device processing.

One embodiment of the fabrication is shown in FIG. 2 where calciumfluoride (CaF₂) is used as the epitaxial insulating interlayer. CaF₂ isan ionically bonded cubic compound with a lattice parameter of 5.46 Å(0.6% larger than Si) and a dielectric constant of about 6.7. CaF₂ growsepitaxially on Si {111} surfaces with abrupt Ca—Si bonding at theinterface providing the necessary charge neutrality. Atomically flatsurfaces can be produced on Si {111} surfaces when grown at substratetemperatures close to 450° C. FIG. 2 shows the epitaxial crystallinealignment forming the coincident lattice between a silicon cross-section12 and a calcium fluoride cross-section 14 with a crystallineorientation 20 along the [111] and [11 2] directions of the siliconlayer. The {111} crystallographic surfaces of CaF₂ 16 are the lowestfree energy surfaces of CaF₂ and they terminate in a stableunreconstructed surface. CaF₂ grows in a layer-by-layer growth modeunder certain conditions enabling the thickness of the layer to becontrolled with atomic scale precision. Although the Si/CaF₂ interfacewill reorder to establish the stable Si—Ca bonding, the two materials donot significantly intermix and are relatively stable in contact witheach other up to their respective desorption temperatures. CaF₂ is alsostable in contact with graphite with graphite crucibles used in thegrowth of high purity bulk CaF₂ crystals. The thermodynamic stability ofthe CaF₂ interlayer with graphene also provides the opportunity tomanipulate the energetics of the graphene growth process to find a selfassembly regime whereby growth is self limiting and results in only onemonolayer of growth.

The embodiment containing CaF₂ interlayers grown on crystalline siliconlayers provides a template that enables the nucleation and growth of thegraphene layer and is non-reactive, thermally stable, electricalinsulating, terminates in atomically flat surfaces, is closely latticematched to Si, and forms a coincident lattice with graphene to controlthe growth orientation. Other embodiments include but are not limited tothe use of Gd₂O₃, SrO, or SrTiO₃ as the epitaxial insulating layer. Inall these embodiments the crystalline structure of the silicon layer ismaintained by the epitaxial insulating interlayer while the interlayerprovides the desired electrical insulation and physical separationbetween the carbon and silicon. In other embodiments, other crystallinesubstrate materials may be similarly mated to graphene by use of otherinterlayer materials. In each case, the crystalline substrate shouldhave an exposed {111} plane that is as near ideal as possible.Preferably, the substrate will be within a fractional degree (e.g., lessthan one degree and preferably less than 0.5 degrees) of the surfacenormal, but may work suitably well when less than about 1-2 degrees ofsurface normal. It is expected that greater than 10 degrees from surfacenormal will result in unsatisfactory results due to an unacceptablenumber of “stair-step” like changes in the surface geometry.

FIG. 3A shows an additional embodiment of the structure depicted in FIG.1 where an additional epitaxial layer 30 has been grown on thecrystalline silicon prior to the deposition of the graphene layer. Theadditional epitaxial layer may be another insulator, conductor, orsemiconductor, but regardless of the electrical properties it shouldmaintain the crystalline symmetry of the crystalline silicon layer andallow for the growth of the epitaxial insulating layer on its surface.Such embodiments could be used to provide a metallic contact for a backgated device structure, or may serve as a diffusion barrier between thesilicon and the epitaxial insulating layer if they are not sufficientlystable.

FIG. 3B shows an embodiment where the additional epitaxial layer hasbeen grown between the epitaxial insulating layer and graphene layer.Likewise the embodiment in FIG. 3C shows a possible embodiment where theadditional epitaxial interlayer is grown on the epitaxial insulatinglayer and then a second epitaxial insulating interlayer is subsequentlygrown on top. An application of such an embodiment would be in backgated transistor structures where it is desired to keep the bottomelectrode electrically isolated from the crystalline silicon layer.

FIG. 3D shows an embodiment similar to the one shown in FIG. 3C, exceptin this embodiment the additional epitaxial layer is patterned eitherin-situ or ex-situ prior to deposition of the second epitaxialinsulating layer. Embodiments consistent with the present invention arenot limited in the number of layers that are included between thecrystalline silicon and the graphene, only that the heterostructure as awhole retains an epitaxial relationship to the crystalline silicon andmaintains a 3n symmetry to support graphene growth to form a coincidentlattice structure.

FIG. 4 shows a flow chart depicting the basic flow of a fabricationprocess 40 consistent with certain example embodiments of the presentinvention starting at 42. At 44, a crystalline substrate is prepared orprovided in which providing a crystalline substrate oriented with a{111} plane surface that is within 10 degrees of surface normal. In oneimplementation, the substrate is a silicon wafer. Such substrate shouldbe clean and free of oxide. At 46 the process proceeds by epitaxiallygrowing an electrically insulating interlayer overlaying the crystallinesubstrate to establish a coincident lattice that mates with the surfacesymmetry of the {111} plane surface to form a thermodynamically stableinterface. This can be done using thermal evaporation, chemical vapordeposition or any other suitable deposition process and serves to builda template compatible with the final layer to be applied at 48. In oneimplementation, the epitaxial layer is substantially calcium fluoride.

At 48, an atomically stable two dimensional crystalline film isdeposited on the epitaxial insulating layer with a coincident latticematch to the insulating interlayer. This film can be formed usinggraphene as disclosed, but other materials such as boron may also besuitable, and other materials will occur to those skilled in the artupon consideration of the present teachings. The growth of the graphenelayer may occur whereby any carbon based species in a solid, liquid,and/or gaseous state is controllably introduced to the surface of theepitaxial layers on the crystalline silicon. The growth conditions areultimately controlled by the sticking coefficient, desorption rate,surface mobility and bond strengths of the source materials in relationto the epitaxial insulating layer structure deposited on the crystallinestructure. Ideal growth occurs in a self limiting regime whereby thegrowth is self terminated after one monolayer has been deposited, butpossible growth mechanisms are not limited to this regime. Growth can beinitiated via chemical vapor deposition, plasma deposition, plasmaassisted chemical vapor deposition, molecular beam epitaxy, thermalevaporation, thermal sublimation, or any related method of producing acontrollable flux of carbon containing molecules in the vicinity of thedesired growth surface. The process then ends at 50.

In the variations depicted in FIG. 3, the process is varied in a mannerthat will be clear to those skilled in the art given the presentteachings in order to create various electronically useful structuressuch as transistors and the like.

Many applications are contemplated for the structure shown including butnot limited to the fabrication of field effect devices where thegraphene layer is used as the conducting channel. Such devices may useeither a back gate design incorporated into the epitaxial insulatedinterlayer or standard metal-oxide layer on the surface. The use ofepitaxial layers permits the growth thickness to be controlled with nearatomic level precision making it easy to achieve reproducibleperformance in device structures.

The fabricated structure is not limited to pure carbon containinggraphene films. The method is also applicable to carbon based filmscontaining impurity atoms introduced into the film to modify itselectrical performance or to other two dimensional structures that maybe discovered with similar physical structures and symmetries to thoseof graphene.

Thus, in certain implementations, a method for fabricating asemiconductor structure involves providing a monocrystalline substrateoriented with a {111} plane surface that is within 10 degrees of surfacenormal; epitaxially growing an electrically insulating interlayeroverlaying the crystalline substrate to establish a coincident latticethat mates with the surface symmetry of the {111} plane surface; anddepositing an atomically stable two dimensional crystalline film on theepitaxial insulating layer with a coincident lattice match to theinsulating interlayer.

In certain implementations, the monocrystalline substrate comprisessubstantially a silicon monocrystalline substrate. In certainimplementations, the interlayer is fabricated of CaF₂. In certainimplementations, the atomically stable two dimensional crystalline filmis predominantly composed of carbon. In certain implementations, theinterlayer is fabricated of a material selected from the groupconsisting of Gd₂O₃, SrO and SrTiO₃. In certain implementations, theinterlayer is fabricated of an epitaxial oxide having a latticestructure suitable for forming a coincident lattice with both thecrystalline substrate and the two dimensional crystalline film. Incertain implementations, at least one additional epitaxial layer isgrown between the silicon substrate and the electrically insultinglayer. In certain implementations, at least one additional epitaxiallayer is grown between the electrically insulting layer and the twodimensional crystalline film. In certain implementations, themonocrystalline substrate is oriented with a {111} plane surface that iswithin 2 degrees of surface normal. In certain implementations, themonocrystalline substrate is oriented with a {111} plane surface that iswithin ½ degree of surface normal. In certain implementations, theinsulating interlayer maintains an epitaxial alignment with thecrystalline silicon layer and has a 3n fold surface symmetry where n isan integer.

Another method for fabricating a semiconductor structure involvesproviding a monocrystalline silicone substrate oriented with a {111}plane surface that is within 2 degrees of surface normal and having anon-oxidized surface; epitaxially growing an electrically insulatinginterlayer selected from the group consisting of CaF₂, Gd₂O₃, SrO andSrTiO₃ overlaying the crystalline substrate to establish a coincidentlattice that mates with surface symmetry of the {111} plane surface; anddepositing an atomically stable two dimensional crystalline filmpredominantly composed of carbon on the epitaxial insulating layer witha coincident lattice match to the insulating interlayer.

In certain implementations, at least one additional epitaxial layer isgrown between the silicon substrate and the electrically insultinglayer. In certain implementations, at least one additional epitaxiallayer is grown between the electrically insulting layer and the twodimensional crystalline film. In certain implementations, themonocrystalline substrate is oriented with a {111} plane surface that iswithin 2 degrees of surface normal. In certain implementations, theinsulating interlayer maintains an epitaxial alignment with thecrystalline silicon layer and has a 3n fold surface symmetry where n isan integer.

A semiconductor structure consistent with certain implementations has amonocrystalline substrate oriented with a {111} plane surface that iswithin 10 degrees of surface normal. An epitaxially grown electricallyinsulating interlayer overlays the crystalline substrate and establishesa coincident lattice that mates with the surface symmetry of the {111}plane surface. An atomically stable two dimensional crystalline filmresides on the epitaxial insulating layer with a coincident latticematch to the insulating interlayer.

In certain implementations, the monocrystalline substrate comprisessubstantially a silicon monocrystalline substrate. In certainimplementations, the interlayer is fabricated of CaF₂. In certainimplementations, the atomically stable two dimensional crystalline filmis predominantly composed of carbon. In certain implementations, theinterlayer is fabricated of a material selected from the groupconsisting of Gd₂O₃, SrO and SrTiO₃. In certain implementations, theinterlayer is fabricated of an epitaxial oxide having a latticestructure suitable for forming a coincident lattice with both thecrystalline substrate and the two dimensional crystalline film. Incertain implementations, at least one additional epitaxial layer isgrown between the silicon substrate and the electrically insultinglayer. In certain implementations, at least one additional epitaxiallayer is grown between the electrically insulting layer and the twodimensional crystalline film. In certain implementations, themonocrystalline substrate is oriented with a {111} plane surface that iswithin 2 degrees of surface normal. In certain implementations, themonocrystalline substrate is oriented with a {111} plane surface that iswithin ½ degrees of surface normal. In certain implementations, theinsulating interlayer maintains an epitaxial alignment with thecrystalline silicon layer and has a 3n fold surface symmetry where n isan integer.

While certain illustrative embodiments have been described, it isevident that many alternatives, modifications, permutations andvariations will become apparent to those skilled in the art in light ofthe foregoing description.

1. A method for fabricating a semiconductor structure, comprising:providing a monocrystalline substrate oriented with a {111} planesurface that is within 10 degrees of surface normal; epitaxially growingan electrically insulating interlayer overlaying the crystallinesubstrate to establish a coincident lattice that mates with the surfacesymmetry of the {111} plane surface; and depositing an atomically stabletwo dimensional crystalline film on the epitaxial insulating layer witha coincident lattice match to the insulating interlayer.
 2. The methodaccording to claim 1, wherein the monocrystalline substrate comprisessubstantially a silicon monocrystalline substrate.
 3. The methodaccording to claim 1, wherein the interlayer is fabricated of CaF₂. 4.The method according to claim 1, wherein the atomically stable twodimensional crystalline film is predominantly composed of carbon.
 5. Themethod according to claim 1, where the interlayer is fabricated of amaterial selected from the group consisting of Gd₂O₃, SrO and SrTiO₃. 6.The method according to claim 1, wherein the interlayer is fabricated ofan epitaxial oxide having a lattice structure suitable for forming acoincident lattice with both the crystalline substrate and the twodimensional crystalline film.
 7. The method according to claim 1,wherein at least one additional epitaxial layer is grown between thesilicon substrate and the electrically insulting layer.
 8. The methodaccording to claim 1, wherein at least one additional epitaxial layer isgrown between the electrically insulting layer and the two dimensionalcrystalline film.
 9. The method according to claim 1, wherein themonocrystalline substrate is oriented with a {111} plane surface that iswithin 2 degrees of surface normal.
 10. The method according to claim 1,wherein the monocrystalline substrate is oriented with a {111} planesurface that is within ½ degree of surface normal.
 11. The methodaccording to claim 1, wherein the insulating interlayer maintains anepitaxial alignment with the crystalline silicon layer and has a 3n foldsurface symmetry where n is an integer.
 12. A method for fabricating asemiconductor structure, comprising: providing a monocrystallinesilicone substrate oriented with a {111} plane surface that is within 2degrees of surface normal and having a non-oxidized surface; epitaxiallygrowing an electrically insulating interlayer selected from the groupconsisting of CaF₂, Gd₂O₃, SrO and SrTiO₃ overlaying the crystallinesubstrate to establish a coincident lattice that mates with surfacesymmetry of the {111} plane surface; and depositing an atomically stabletwo dimensional crystalline film predominantly composed of carbon on theepitaxial insulating layer with a coincident lattice match to theinsulating interlayer.
 13. The method according to claim 12, wherein atleast one additional epitaxial layer is grown between the siliconsubstrate and the electrically insulting layer.
 14. The method accordingto claim 12, wherein at least one additional epitaxial layer is grownbetween the electrically insulting layer and the two dimensionalcrystalline film.
 15. The method according to claim 12, wherein themonocrystalline substrate is oriented with a {111} plane surface that iswithin 2 degrees of surface normal.
 16. The method according to claim12, wherein the insulating interlayer maintains an epitaxial alignmentwith the crystalline silicon layer and has a 3n fold surface symmetrywhere n is an integer.
 17. A semiconductor structure, comprising: amonocrystalline substrate oriented with a {111} plane surface that iswithin 10 degrees of surface normal; an epitaxially grown electricallyinsulating interlayer overlaying the crystalline substrate thatestablishes a coincident lattice that mates with the surface symmetry ofthe {111} plane surface; and an atomically stable two dimensionalcrystalline film on the epitaxial insulating layer with a coincidentlattice match to the insulating interlayer.
 18. The semiconductorstructure according to claim 17, wherein the monocrystalline substratecomprises substantially a silicon monocrystalline substrate.
 19. Thesemiconductor structure according to claim 17, wherein the interlayer isfabricated of CaF₂.
 20. The semiconductor structure according to claim17, wherein the atomically stable two dimensional crystalline film ispredominantly composed of carbon.
 21. The semiconductor structureaccording to claim 17, where the interlayer is fabricated of a materialselected from the group consisting of Gd₂O₃, SrO and SrTiO₃.
 22. Thesemiconductor structure according to claim 17, wherein the interlayer isfabricated of an epitaxial oxide having a lattice structure suitable forforming a coincident lattice with both the crystalline substrate and thetwo dimensional crystalline film.
 23. The semiconductor structureaccording to claim 17, wherein at least one additional epitaxial layeris grown between the silicon substrate and the electrically insultinglayer.
 24. The semiconductor structure according to claim 17, wherein atleast one additional epitaxial layer is grown between the electricallyinsulting layer and the two dimensional crystalline film.
 25. Thesemiconductor structure according to claim 17, wherein themonocrystalline substrate is oriented with a {111} plane surface that iswithin 2 degrees of surface normal.
 26. The semiconductor structureaccording to claim 17, wherein the monocrystalline substrate is orientedwith a {111} plane surface that is within ½ degrees of surface normal.27. The semiconductor structure according to claim 17, wherein theinsulating interlayer maintains an epitaxial alignment with thecrystalline silicon layer and has a 3n fold surface symmetry where n isan integer.